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Board Components
Ethernet
MAC/PHY (U4) &
RJ45 Connector
(RJ1)
The LAN91C111 chip (U4) is a 10/100 Ethernet media access control and
physical interface (MAC/PHY) chip. The control pins of U4 are
connected to the FPGA so that Nios II systems can access Ethernet
networks via the RJ-45 connector (RJ1) as shown in Figure 2–4 . The
Nios II development tools include hardware and software components
that allow Nios II processor systems to communicate with the
LAN91C111 Ethernet device.
Figure 2–4. Ethernet RJ-45 Connector
U4
RJ1
Refer to Table 2–9 for connections between the FPGA and the MAC/PHY
device.
1
The Ethernet MAC/PHY device shares both address and data
connections with the flash memory.
Table 2–9. Ethernet MAC/PHY Pin Table
FPGA Pin
E26
J17
F18
G18
D18
E18
A19
B19
D20
D14
Y15
AA15
41
43
40
45
38
37
42
46
35
36
34
29
U4 Pin
Pin Function
Address Enable
Synchronous Ready
VL Bus Access
Local Device
IO Char Ready
Address Strobe
Local Bus Clock
Ready/Return
Bus Cycle
Write/Read
Bus Chip Select
Interrupt
Board Net Name (1)
enet_aen
enet_srdy_n
enet_vlbus_n
enet_ldev_n
enet_iochrdy
enet_ads_n
enet_lclk
enet_rdyrtn_n
enet_cycle_n
enet_w_r_n
enet_datacs_n
enet_intr0
Altera Corporation
May 2007
Reference Manual 2–13
Nios Development Board Cyclone II Edition
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